Probabilistic Transfer Matrix with mixed Binary-Decimal Coding for Logic Circuit Reliability Analysis

Technology scale leads to increasing the vulnerability of new integrated logic circuits. The highenergy neutrons (present in terrestrial cosmic radiation) and alpha particles (that originate from impurities in the packagingmaterials) play important role in occurrence of transient faults which are e®ective factor for designing reliable integrated circuits. Thus, a fast and scalable method to obtain accurate reliability value is an issue to have a dependable logic circuit design. In this paper, a new fast and scalable method is proposed to calculate the circuit reliability in which the e®ects of nested reconvergent paths, as a main source of inaccuracy, is considered. In the presence of reconverging signals a binary probability matrix is used to resolve signals correlation problem and increase the accuracy of the obtained reliability. Also a new mixed binary-decimal code allocation is proposed to increase the scalability of the method and reduce the complexity of calculation. Simulation results show that our proposed solution is a fast method with less complexity and also gives an accurate reliability value in comparison with other methods.